As memory chip manufacturers strive to decrease die size, and increase capacity and speed they must contend with an increased percentage of defective, or faulty memory cells. Different approaches have been taken to overcome detected memory cell defects. One approach has been to “repair” out a defective memory column or row by “flagging” the defective column or row and using redundant columns or rows of memory cells that are substituted for defective columns or rows. A defective region is marked as defective by blowing fuses, or anti-fuses, or lasers are used to etch circuits, to set latches which remap the defective column or row to a non-defective fully-operable redundant column or row. With this re-mapping, attempts to address the defective column or row will be redirected to address the redundant column or row known to be properly working.
Referring to FIG. 1, a portion of a conventional column redundancy repair fuse array 10 for a flash memory is shown. Fuse Array 10 contains a series of eight fuse sets 100, although only two fuse sets, Fuse Set0 and Fuse Set7, are shown for simplicity. The eight fuse sets 100 permit the redirecting of eight defective addressed columns to eight operable redundant columns. Each fuse set 100 contains fourteen fuses 102, Fuse0 . . . Fuse13, although only fuses Fuse0 and Fuse13 are shown in FIG. 1 for simplicity. Each fuse 102 stores one bit of an address and contains a latch 118 formed of a pair of inverters 110a and 110b. An Fbias control line 104 acts on transistors 111, 111′ which form an isolation circuit for the latch 118. When the Fbias control line 104 is enabled and word line WL0 106 is enabled, a complementary bit pattern stored in flash transistors 113, 113′, representing a stored address bit is written to latch 118. Disabling the Fbias 104 isolates the latch 118 from the storage transistors 113, 113′ for programming of transistors 113, 113′.
Thus, each fuse 102, e.g. Fuse0, in FIG. 1, stores in the associated latch 118 one address bit that is used for comparison with a corresponding bit of an incoming column address. For example, the first bit, Address Bit0, of an incoming address will be input to XOR gate 114 which compares the address bit to the address bit stored in latch 118. The result of the comparison is output through conductive line 116. If the logic value of Address Bit0 is the same as the logic value of stored in latch 118 then conductive line 116 will carry a logic value of one. If they are not the same, then conductive line 116 will carry a logic value of zero. The resulting output of each of the Fuse0 . . . Fuse13 in the fuse set0 100 are then compared in AND gate 150, to see if all of the incoming address bits are the same as all of the corresponding latch stored values. Each fuse set 100 is associated with a unique redundant column in a memory array. Thus, if there is an address match detected by AND gate 150 for a memory access a redundant column is utilized in place of the original defective column.
The problem with this approach is that since each fuse set 100 is permanently set with the address of a defective column, the number of defective columns which can be repaired is limited by the number of fuse sets 100 fabricated on the die. In the prior art example of FIG. 1, only eight defective columns may be re-addressed. Additionally, fuse arrays 10 consume die space. Accordingly, adding more fuse sets 100 to provide increased repair possibilities unduly increases die size.